The present invention relates to a receiving device or a reproducing device provided in an information transmitting and communicating apparatus or an information storing and reproducing apparatus and more particularly to a maximum likelihood decoding device or a method of implementing a general composition of a maximum likelihood decoding circuit widely used in various information processing and signal processing devices.
In order to improve low-quality transmission or reliability of data reproduction from a recording and reproducing signal in a fast information communications system or a high-density information recording and reproducing system, there has been widely used an error correction demodulation technique based on a data decoding technique and a convolutional encoding technique that utilizes the MLSD (Maximum Likelihood Sequence Detection).
This maximum likelihood sequence detection is a technique of suppressing a probability of causing an error in a decoded code sequence to a minimum by estimating the decoded code sequence in time series based on the storage characteristic or the correlation of the decoded data. In this technique, when a received signal sequence {Y(n)} (n denotes an integer for indicating a discrete signal occurrence sequence and time) is given into the decoding input, the maximum likelihood sequence of receiving {Y(n)} (the maximum likelihood sequence) is selected from all possible transmission information (code) sequences {X(n)} and then the maximum likelihood sequence is outputted as the decoded information (code) sequence {Z(n)}. In other words, given all possible sequences of a certain receiving signal sequence {Y(n)}, on the assumption of a certain transmitting sequence {X(n)}, the transmitting sequence {X(n)} is selected so that the a-posteriori probability P ({Y(n)}/{X(n)}) before and after the receiving signal sequence {Y(n)} is received is made maximum, for estimating the maximum likelihood sequence of the decoded sequence {Z(n)}. At this time, the transmitting sequence {X(n)} is estimated not independently but on the context. This kind of maximum likelihood sequence detection provides the most excellent decoding error probability in the decoding operation as keeping a correct decision probability P ({X(n)} and {Z(n)}) (the probability of coinciding the transmitting sequence {X(n)} with the decoded sequence {Z(n)}) in the condition of transmitting all possible transmission sequences {X(n)} at equal probabilities, in other words, in the condition of giving no information about the transmitting probability of each transmitting sequence {X(n)}.
This maximum likelihood sequence detection is efficiently realized by using a dynamically programing Viterbi algorithm. The papers about the maximum likelihood sequence detection and the Viterbi algorithm are, for example, G. D. Forney, xe2x80x9cThe Viterbi Algorithmxe2x80x9d, Proceedings of the IEEE, vol. 61, No.3, March 1973, pp.268 to 278 and G. Ungerbock, xe2x80x9cAdaptive Maximum Likelihood Receiver for Carrier-Modulated Data Transmission Systemsxe2x80x9d, IEEE Transactions on Communications, vol. COM-22, No.5, May 1974, pp.624 to 638. These papers discuss the receiver apparatus arranged to use the maximum likelihood sequence detection or its partial basic arrangement. Further, the actual implementation of the Viterbi Algorithm is discussed in detail in Hui-Ling Lou, xe2x80x9cImplementing the Viterbi Algorithmxe2x80x9d, IEEE Signal Processing Magazine, Sept. 1995, pp.42-52 and G. Fettweis and H. Meyr, xe2x80x9cHigh-speed Parallel Viterbi Decoding: Algorithm and VLSI-architecturexe2x80x9d, IEEE Communications Magazine, May 1991, pp. 46 to 55.
The maximum likelihood sequence detection arranged to use this kind of Viterbi algorithm is executed to select the sequence having the maximum receiving likelihood (the maximum likelihood sequence) based on the context of the receiving signal sequences and output it as the most probable decoded information (code) sequence. This sequence corresponds to the decoded result. Hence, this detection needs to prepare a survivor path sequence history storing circuit (path memory) for storing the candidate sequences (survivor path sequences) of the maximum likelihood sequences to be progressively narrowed, sequentially updating the content based on the comparative operational result of the likelihood, and deciding the maximum likelihood decoded result. From a viewpoint of the principle of the Viterbi algorithm, this path sequence history storing circuit is required to store information about a long survivor path sequence history, which should be long enough to secure the decoding reliability against the noises in the receiving signal sequence. For implementing the Viterbi algorithm, it is necessary to prepare the survivor path sequence storing circuit (path memory) having a massive volume for corresponding to the required decoding reliability.
For example, a small-sized information processing instrument representatively such as a portable information terminal is earnestly required to reduce the power consumption for the purpose of suppressing the consumption of a cell and extending the operating time. In the case of applying the maximum likelihood decoding technique to a signal processing system included in this type of information processing instrument, the reduction of the electric power consumed in the path memory is one of the significant technical issues.
It is an object of the present invention to reduce the electric power consumed in a relatively large-scale survivor path sequence storing circuit (path memory) included in the maximum likelihood decoding circuit or the maximum likelihood decoding device.
It is an object of the present invention to provide a decoding circuit to be mounted into a relatively small-sized information processing instrument requested to lower the power consumption.
It is still another object of the present invention to provide a decoding circuit which enables to control and operate the instrument to be built into the system from various points of view.
It is a further object of the present invention to provide a decoding circuit which may improve flexibility in design, integrity in mounting, and yields in packing the decoding circuit to the semiconductor integrated circuit.
It is a still further object of the present invention to provide an information processing apparatus which is arranged to reduce the power consumption of the relatively large-scale survivor path sequence storing circuit (path memory) included in the mounted maximum likelihood decoding circuit or maximum likelihood decoding device, for realizing the reduction of the power consumption of the overall apparatus.
It is another object of the present invention to provide an information processing apparatus which is arranged to consume a low electric power and easily implement the high reliability based on the maximum likelihood decoding.
It is another object of the present invention to provide an information processing apparatus which may be controlled and prompted from various points of view and based on the information obtained from the mounted decoding circuit.
It is another object of the present invention to provide an information processing apparatus which is arranged to improve flexibility in design and integrity in packaging when packaging the mounted decoding circuit for doing the maximum likelihood decoding operation to a semiconductor integrated circuit.
The present invention utilizes convergence of the survivor path sequence information in the Viterbi algorithm. Of plural pieces of survivor path sequence information stored in the survivor path sequence storing circuit, the survivor path sequence information pieces corresponding to the convergence-completed portion are all identical with each other. The stored content is not varied from when the convergence is completed to when the information is outputted as the decoded result. In the actual decoding process, the phenomenon that the survivor path information pieces are not still convergent in the almost length of the prepared survivor path sequence storing circuit depends on the expected decoding reliability and hence is brought about so rarely. Normally, the survivor path sequence information is quickly and concentratively converted at a quite early stage of the length of the prepared survivor path sequence storing circuit. The present invention uses the property of the convergence of the survivor path sequence information for lowering a frequency of updating the stored content of the storing element of the survivor path sequence storing circuit and a utilization rate of the circuit, thereby reducing the power consumption. For this purpose, the present invention provides means for composing the survivor path sequence storing circuit for constantly holding plural candidates of the survivor path sequence information for each receiving signal sequence time in the same storage element block composed of plural storage elements and recursively updating the survivor path sequence information among the storage elements, for the purpose of concretely implementing the reduction of the circuit utilization rate. Further, for enhancing the reducing effect of the power consumption, the present invention provides means for predicting the storage element block in which the convergence of the survivor path sequence information is completed or the storage elements for holding the survivor path sequence information that is not necessary later than the present time and stopping a synchronous clock signal for starting the update operation of the predicted storage elements.